Wafer-Level SSD – New approach to mass storage production at Kioxia

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Shigeo Oshima spoke about wafer-level SSDs during the online VLSI Symposium 2020 in a presentation on the future of flash memory. The chief engineer of the NAND flash manufacturer Kioxia, formerly Toshiba Memory thus underscored the group’s claim in the development of innovative storage solutions parallel to the acquisition of the SSD division of Lite-On.
Until now, technical innovations in SSDs have been achieved primarily through additional cell layers such as 3D NAND or PLC NAND, which have further increased storage capacities. However, the manufacturing process of the various NAND types is identical. In the first step, chips are cut from a silicon wafer similar to those used in CPU and GPU production. These are then placed in a chip housing (packaging), which is then installed on the boards of SSDs and other storage media.
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